MC9S12T64 Datasheet, PDF (483/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Low Power Mode Options
Low Power Mode Options
SPI in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control
register clear, the SPI system is in a low-power, disabled state. SPI
registers can still be accessed, but clocks to the core of this module are
disabled.
SPI in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit
in SPI control register 2.
• If SPISWAI is clear, the SPI operates normally when the CPU is in
wait mode
• If SPISWAI is set, SPI clock generation ceases and the SPI
module enters a power conservation state when the CPU is in wait
mode.
– If SPISWAI is set and the SPI is configured for master, any
transmission and reception in progress stops at wait mode
entry. The transmission and reception resumes when the SPI
exits wait mode.
– If SPISWAI is set and the SPI is configured as a slave, any
transmission and reception in progress continues if the SCK
continues to be driven from the master. This keeps the slave
synchronized to the master and the SCK.
If the master transmits several bytes while the slave is in wait
mode, the slave will continue to send out bytes consistent with
the its operation mode at the start of wait mode (i.e. If the slave
is currently sending its SPIDR to the master, it will continue to
send the same byte. Else if the slave is currently sending the
last received byte from the master, it will continue to send each
previous master byte).
NOTE:
Care must be taken when expecting data from a master while the slave
is in wait or stop mode. Even though the shift register will continue to
operate, the rest of the SPI is shut down (i.e. a SPIF interrupt will not be
generated until exiting stop or wait mode). Also, the byte from the shift
Serial Peripheral Interface (SPI)
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MC9S12T64Revision 1.1.1