MC9S12T64 Datasheet, PDF (449/608 Pages) Motorola, Inc – Specification

Framing Errors
Baud Rate
Tolerance
Slow Data
Tolerance
Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
Functional Description
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming frame, it sets the framing error flag, FE, in SCI
status register 1 (SCIxSR1). A break character also sets the FE flag
because a break character has no stop bit. The FE flag is set at the same
time that the RDRF flag is set.
A transmitting device may be operating at a baud rate below or above
the receiver baud rate. Accumulated bit time misalignment can cause
one of the three stop bit data samples (RT8, RT9, and RT10) to fall
outside the actual stop bit. A noise error will occur if the RT8, RT9, and
RT10 samples are not all the same logical values. A framing error will
occur if the receiver clock is misaligned in such a way that the majority
of the RT8, RT9, and RT10 stop bit samples are a logic zero.
As the receiver samples an incoming frame, it re-synchronizes the RT
clock on any valid falling edge within the frame. Resynchronization
within frames will correct a misalignment between transmitter bit times
and receiver bit times.
Figure 87 shows how much a slow received frame can be misaligned
without causing a noise error or a framing error. The slow stop bit begins
at RT8 instead of RT1 but arrives in time for the stop bit data samples at
RT8, RT9, and RT10.
RECEIVER
RT CLOCK
MSB
STOP
DATA
SAMPLES
Figure 87 Slow Data
For an 8-bit data character, data sampling of the stop bit takes the
receiver 9 bit times x 16 RT cycles +10 RT cycles =154 RT cycles.
Serial Communications Interface (SCI)
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MC9S12T64Revision 1.1.1