MC9S12T64 Datasheet, PDF (299/608 Pages) Motorola, Inc – Specification

System Clocks
Generator
Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Functional Description
PLLSEL or SCM
PHASE
LOCK
LOOP
PLLCLK
1
0
EXTAL
OSCCLK
OSCILLATOR
XTAL
Clock
Monitor
SCM
1
0
SYSCLK
WAIT(SYSWAI),
STOP
WAIT(RTIWAI),
STOP(PSTP,PRE),
RTI enable
WAIT(COPWAI),
STOP(PSTP,PCE),
COP enable
WAIT(SYSWAI),
STOP
WAIT(CWAI,SYSWAI),
STOP
÷2
CLOCK PHASE
GENERATOR
RTI
COP
Core Clock
Bus Clock
Oscillator
Clock
Gating
Condition
= Clock Gate
STOP(PSTP)
Oscillator *
Clock
(running during
Pseudo Stop Mode
* This clock is not used in the current MCU.
Figure 47 Clock Generator
The clock generator creates the clocks used in the MCU (see Figure 47).
The gating condition placed on top of the individual clock gates indicates
the dependencies of different modes (STOP, WAIT) and the setting of
the respective configuration bits. For example, a WAIT(SYSWAI) gating
condition states that when the SYSWAI bit is set, the correspondent gate
will be disabled during WAIT mode.
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1