MC9S12T64 Datasheet, PDF (399/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
Input Control Pulse
Accumulators
Register (ICPAR)
Register offset: $0068
Bit 7
Read:
0
Write:
Reset:
0
6
5
4
0
0
0
0
0
0
= Reserved or unimplemented
3
PA3EN
0
2
PA2EN
0
1
PA1EN
0
Bit 0
PA0EN
0
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if
PAEN in PACTL is cleared. If PAEN is set, PA3EN and PA2EN have no
effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if
PBEN in PBCTL is cleared. If PBEN is set, PA1EN and PA0EN have no
effect.
Read or write any time.
PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable
1 = 8-Bit Pulse Accumulator is enabled.
0 = 8-Bit Pulse Accumulator is disabled.
NOTE:
The input capture edge circuits of 8-bit pulse accumulators are
configured with control bits EDGnA and EDGnB in the TCTL4 register
(see page 386).
Delay Counter
Control Register
(DLYCT)
Register offset: $0069
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
DLY1
DLY0
Write:
Reset:
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Enhanced Capture Timer (ECT)
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MC9S12T64Revision 1.1.1