MC9S12T64 Datasheet, PDF (152/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Port E Data
Direction Register
(DDRE)
Address Offset: $0009
Bit 7
Read:
BIT 7
Write:
Reset:
0
6
5
4
3
2
1
Bit 0
BIT 1
BIT 0
6
5
4
3
BIT 2
0
0
0
0
0
0
0
= Unimplemented or reserved
Read and write: anytime (provided this register is in the map).
Data Direction Register E is associated with Port E. For bits in Port E
that are configured as general purpose I/O lines, DDRE determines
the primary direction of each of these pins. A “1” causes the
associated bit to be an output and a “0” causes the associated bit to
be an input. Port E bit 1 (associated with IRQ) and bit 0 (associated
with XIRQ) cannot be configured as outputs. Port E, bit 1, and bit 0
can be read regardless of whether the alternate interrupt function is
enabled. The value in a DDR bit also affects the source of data for
reads of the corresponding PORTE register. If the DDR bit is zero
(input) the buffered pin input is read. If the DDR bit is one (output) the
associated port data register bit state is read.
This register is not in the on-chip map in peripheral mode. It is also not
in the map in expanded modes while the EME control bit is set.
DDRE7–2 — Data Direction Port E
1 = Configure the corresponding I/O pin as an output
0 = Configure the corresponding I/O pin as an input
CAUTION:
It is unwise to write PORTE and DRRE as a word access. If you are
changing PORT E pins from being inputs to outputs, the data may have
extra transitions during the write. It is best to initialize PORTE before
enabling as outputs.
MC9S12T64Revision 1.1.1
Multiplexed External Bus Interface (MEBI)
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