MC9S12T64 Datasheet, PDF (388/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
1 = Counter reset by a successful output compare 7
0 = Counter reset inhibited and counter free runs
If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously.
If TC7 = $FFFF and TCRE = 1, TOF in TFLG2 (see page 389) will
never be set when TCNT is reset from $FFFF to $0000.
PR2, PR1, PR0 — Timer Prescaler Select
These three bits specify the number of ÷2 stages that are to be
inserted between the bus clock and the main timer counter.
Table 67 Prescaler Selection
PR2
PR1
PR0
Prescale Factor
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
Main Timer
Interrupt Flag 1
(TFLG1)
Register offset: $004E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
Write:
Reset:
0
0
0
0
0
0
0
0
TFLG1 indicates when interrupt conditions have occurred.
Read anytime.
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
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