MC9S12T64 Datasheet, PDF (430/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
1 = Byte transferred to transmit shift register; transmit data register
empty
0 = No byte transferred to transmit shift register
TC — Transmit Complete Flag
TC is set low when there is a transmission in progress or when a
preamble or break character is loaded. TC is set high when the TDRE
flag is set and no data, preamble, or break character is being
transmitted. When TC is set, the TXD out signal becomes idle (logic
1). Clear TC by reading SCI status register 1 (SCIxSR1) with TC set
and then writing to SCI data register low (SCIxDRL). TC is cleared
automatically when data, preamble, or break is queued and ready to
be sent. TC is cleared in the event of a simultaneous set and clear of
the TC flag (transmission not complete).
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full Flag
RDRF is set when the data in the receive shift register transfers to the
SCI data register. Clear RDRF by reading SCI status register 1
(SCIxSR1) with RDRF set and then reading SCI data register low
(SCIxDRL).
1 = Received data available in SCI data register
0 = Data not available in SCI data register
IDLE — Idle Line Flag
IDLE is set when 10 consecutive logic 1s (if M=0) or 11 consecutive
logic 1s (if M=1) appear on the receiver input. Once the IDLE flag is
cleared, a valid frame must again set the RDRF flag before an idle
condition can set the IDLE flag.Clear IDLE by reading SCI status
register 1 (SCIxSR1) with IDLE set and then reading SCI data register
low (SCIxDRL).
1 = Receiver input has become idle
0 = Receiver input is either active now or has never become active
since the IDLE flag was last cleared
NOTE: When the receiver wakeup bit (RWU) is set, an idle line condition does
not set the IDLE flag.
MC9S12T64Revision 1.1.1
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com