MC9S12T64 Datasheet, PDF (476/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Data reception is double buffered. Data is shifted serially into the SPI
shift register during the transfer and is transferred to the parallel SPI data
register after the last bit is shifted in.
After the 16th (last) SCK edge:
• Data that was previously in the master SPI data register should
now be in the slave data register and the data that was in the slave
data register should be in the master.
• The SPIF flag in the SPI status register is set indicating that the
transfer is complete.
Figure 94 is a timing diagram of an SPI transfer where CPHA = 0. SCK
waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may
be interpreted as a master or slave timing diagram since the SCK, MISO,
and MOSI pins are connected directly between the master and the slave.
The MISO signal is the output from the slave and the MOSI signal is the
output from the master. The SS pin of the master must be either high or
reconfigured as a general-purpose output not affecting the SPI.
MC9S12T64Revision 1.1.1
Serial Peripheral Interface (SPI)
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