MC9S12T64 Datasheet, PDF (366/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM8B8C)
are concatenated, and channel 1 when channels 0 and 1 are
concatenated. The resulting PWM is output to the pins of the
corresponding low order 8-bit channel as also shown in Figure 66. The
polarity of the resulting PWM output is controlled by the PPOLx bit of the
corresponding low order 8-bit channel as well.
Once concatenated mode is enabled (CONxx bits set in PWMCTL
register) then enabling/disabling the corresponding 16-bit PWM channel
is controlled by the low order PWMEx bit. In this case, the high order
bytes PWMEx bits have no effect and their corresponding PWM output
is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit
access or writes to either the low or high order byte of the counter will
reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
Either left aligned or center aligned output mode can be used in
concatenated mode and is controlled by the low order CAEx bit. The
high order CAEx bit has no effect.
The table shown below is used to summarize which channels are used
to set the various control bits when in 16-bit mode.
Table 63 16-bit Concatenation Mode Summary
CONxx
CON67
CON45
CON23
CON01
PWMEx
PWME7
PWME5
PWME3
PWME1
PPOLx
PPOL7
PPOL5
PPOL3
PPOL1
PCLKx
PCLK7
PCLK5
PCLK3
PCLK1
CAEx
CAE7
CAE5
CAE3
CAE1
PWMx
OUTPUT
PWM7
PWM5
PWM3
PWM1
MC9S12T64Revision 1.1.1
Pulse Width Modulator (PWM8B8C)
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