MC9S12T64 Datasheet, PDF (36/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Table 3 Addressing Mode Summary (Continued)
Addressing Mode
Indexed
(16-bit offset)
Indexed-indirect
(16-bit offset)
Indexed-indirect
(D accumulator offset)
Source Form
INST oprx16,xysp
INST [oprx16,xysp]
INST [D,xysp]
Abbreviation
Description
IDX2
Effective address is the value in X, Y, SP, or PC plus a
16-bit constant offset.
[IDX2]
The value in X, Y, SP, or PC plus a 16-bit constant
offset points to the effective address.
[D,IDX]
The value in X, Y, SP, or PC plus the value in D points
to the effective address.
Instruction Set Overview
All memory and I/O are mapped in a common 64K byte address space,
allowing the same set of instructions to access memory, I/O, and control
registers. Load, store, transfer, exchange, and move instructions
facilitate movement of data to and from memory and peripherals.
There are instructions for signed and unsigned addition, division and
multiplication with 8-bit, 16-bit, and some larger operands.
Special arithmetic and logic instructions aid stacking operations,
indexing, BCD calculation, and condition code register manipulation.
There are also dedicated instructions for multiply and accumulate
operations, table interpolation, and specialized mathematical
calculations for fuzzy logic operations.
A summary of the CPU instruction set is given in Figure 4 below. A
detailed overview of the entire instruction set is covered in the HCS12
Core User Guide.
Source Form
ABA
ABXSame as LEAX B,X
ABYSame as LEAY B,Y
Table 4 Instruction Set Summary
Operation
Add B to A; (A)+(B)⇒A
Add B to X; (X)+(B)⇒X
Add B to Y; (Y)+(B)⇒Y
Address
Machine
Mode Coding (Hex)
INH
18 06
IDX
1A E5
IDX
19 ED
Access Detail
OO
Pf
Pf
SXHINZVC
––∆–∆∆∆∆
––––––––
––––––––
MC9S12T64Revision 1.1.1
Central Processing Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com