MC9S12T64 Datasheet, PDF (513/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Analog to Digital Converter (ATD)
Functional Description
Table 95 gives a brief description of the different combinations of control bits
and their affect on the external trigger function.
ETRIGLE
X
X
0
0
1
1
Table 95 External Trigger Control Bits
ETRIGP
X
X
0
1
0
1
ETRIGE
0
0
1
1
1
1
SCAN
0
1
X
X
X
X
Description
Ignores external trigger. Performs
one conversion sequence and
stops.
Ignores external trigger. Performs
continuous conversion
sequences.
Falling edge triggered. Performs
one conversion sequence per
trigger.
Rising edge triggered. Performs
one conversion sequence per
trigger.
Trigger active low. Performs
continuous conversions while
trigger is active.
Trigger active high. Performs
continuous conversions while
trigger is active.
During a conversion, if additional active edges are detected the overrun
error flag ETORF is set.
In either level or edge triggered modes, the first conversion begins when
the trigger is received. In both cases, the maximum latency time is one
Bus Clock cycle plus any skew or delay introduced by the trigger
circuitry.
NOTE: The conversion results for the external trigger ATD channel 7 have no
meaning while external trigger mode is enabled.
Once ETRIGE is enabled, conversions cannot be started by a write to
ATDCTL5, but rather must be triggered externally.
If the level mode is active and the external trigger both de-asserts and
re-asserts itself during a conversion sequence, this does not constitute
an overrun. Therefore, the flag is not set. If the trigger is left asserted in
Analog to Digital Converter (ATD)
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MC9S12T64Revision 1.1.1