MC9S12T64 Datasheet, PDF (578/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Electrical Characteristics
Reset, Oscillator and PLL Characteristics
This section summarizes the electrical characteristics of the various
startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
Startup
Table 116 summarizes several startup characteristics explained in this
section. Detailed description of the startup behavior can be found in the
Clocks and Reset Generator (CRG) section in page 271.
Table 116 Startup Characteristics
Conditions are shown in Table 106 unless otherwise noted
Num
Rating
Symbol Min
Typ
Max Unit
1 Reset input pulse width, minimum input time
2 Startup from Reset
3 Interrupt pulse width, IRQ edge-sensitive mode
4 Wait recovery startup time
5 Low-voltage detector reset release level
6 Low voltage detection level
7 Low-voltage detector reset/recover hysteresis
8
POR rearm level ⁽¹⁾
9 POR rise time ramp rate ⁽²⁾
1. Maximum is highest voltage that POR is guaranteed.
PW_RSTL
2
n_RST
192
PW_IRQ
20
t_WRS
V_LVRR
V_LVR
3.9
V_LVHYS
V_POR
0
R_POR
t_osc
196
n_osc
ns
14
t_bus
4.75
V
V
200
mV
100
mV
0.035 V/ms
2. If minimum V_DD is not reached before the internal POR reset is released, RESET must be driven low externally until mini-
mum V_DD is reached.
POR and
Low-voltage
detector (LVD)
Reset
The release level V_LVRR and the detection level V_LVR are derived from
the V_DDR, while the rearm level V_POR is derived from the V_DD. They are
also valid if the device is powered externally.
External Reset
When external reset is asserted for a time greater than PW_RSTL the CRG
module generates an internal reset, and the CPU starts fetching the
MC9S12T64Revision 1.1.1
Electrical Characteristics
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