MC9S12T64 Datasheet, PDF (286/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
1 = Core clock stops in Wait Mode.
0 = Core clock keeps running in Wait Mode.
RTIWAI — RTI stops in WAIT Mode Bit
Write: anytime
1 = RTI stops and initializes the RTI dividers whenever the part
goes into Wait Mode.
0 = RTI keeps running in Wait Mode.
COPWAI — COP stops in WAIT Mode Bit
Write: once
1 = COP stops and initializes the COP dividers whenever the part
goes into Wait Mode.
0 = COP keeps running in Wait Mode.
CRG PLL Control
Register (PLLCTL)
Address Offset: $003A
Bit 7
Read:
CME
Write:
Reset:
1
This register controls the PLL functionality.
6
5
4
3
2
0
PLLON
AUTO
ACQ
PRE
1
1
1
0
0
1
0
PCE
SCME
0
1
Read: anytime.
Write: refer to each bit for individual write conditions.
CME — Clock Monitor Enable Bit
Write: anytime except when SCM = 1
CME enables the clock monitor.
1 = Clock monitor is enabled. Slow or stopped clocks will cause a
clock monitor reset sequence or Self Clock Mode.
0 = Clock monitor is disabled.
NOTE: Operating with CME=0 will not detect any loss of clock. In case of poor
clock quality this could cause unpredictable operation of the MCU!
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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