MC9S12T64 Datasheet, PDF (163/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Functional Description
When internal visibility is enabled (IVIS=1), certain internal cycles will be
blocked from going external to prevent possible corruption of external
devices. Specifically, during cycles when the BDM is selected, R/W will
remain high, data will maintain its previous state, and address and
LSTRB pins will be updated with the internal value. During CPU no
access cycles when the BDM is not driving, R/W will remain high, and
address, data and the LSTRB pins will remain at their previous state.
External Visibility
Of Instruction
Queue
The instruction queue buffers program information and increases
instruction throughput. The queue consists of three 16-bit stages.
Program information is always fetched in aligned 16-bit words. Normally,
at least three bytes of program information are available to the CPU
when instruction execution begins.
Program information is fetched and queued a few cycles before it is used
by the CPU. In order to monitor cycle-by-cycle CPU activity, it is
necessary to externally reconstruct what is happening in the instruction
queue.
Two external pins, IPIPE[1:0], provide time-multiplexed information
about data movement in the queue and instruction execution. To
complete the picture for system debugging, it is also necessary to
include program information and associated addresses in the
reconstructed queue.
The instruction queue and cycle-by-cycle activity can be reconstructed
in real time or from trace history captured by a logic analyzer. However,
neither scheme can be used to stop the CPU at a specific instruction. By
the time an operation is visible outside the system, the instruction has
already begun execution. A separate instruction tagging mechanism is
provided for this purpose. A tag follows the information in the queue as
the queue is advanced. During debugging, the CPU enters active
background debug mode when a tagged instruction reaches the head of
the queue, rather than executing the tagged instruction. For more
information about tagging, refer to Instruction Tagging in page 544.
Instruction Queue The IPIPE[1:0] signals carry time-multiplexed information about data
Status Signals
movement and instruction execution during normal operation. The
Multiplexed External Bus Interface (MEBI)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1