MC9S12T64 Datasheet, PDF (468/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
SPI Status Register
(SPISR)
Address Offset: $00DB
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIF
0
SPTEF
MODF
0
0
0
0
Write:
Reset:
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Read: anytime
Write: has no meaning or effect
SPIF — SPI Interrupt Flag
This bit is set after the eighth SCK cycle in a data transfer and is
cleared by reading the SPISR register (with SPIF set) followed by a
read access to the SPI data register.
1 = New data Copied to SPIDR
0 = Transfer not yet complete
SPTEF — SPI Transmit Empty Interrupt Flag
NOTE: There is an errata information about the SPTEF flag. See MC9S12T64
Errata Sheet for details.
This bit is set when there is room in the transmit data buffer. It is
cleared by reading SPISR with SPTEF set, followed by writing a data
value to the transmit buffer at SPIDR. SPISR must be read with
SPTEF=1 before writing data to SPIDR or the SPIDR write will be
ignored. SPTEF generates an SPTEF CPU interrupt request if the
SPTIE bit in the SPICR1 is also set. SPTEF is automatically set when
a data byte transfers from the transmit buffer into the transmit shift
register. For an idle SPI (no data in the transmit buffer or the shift
register and no transfer in progress), data written to SPIDR is
transferred to the shifter almost immediately so SPTEF is set within
two bus cycles allowing a second 8-bit data value to be queued into
the transmit buffer. After completion of the transfer of the value in the
shift register, the queued value from the transmit buffer will
automatically move to the shifter and SPTEF will be set to indicate
MC9S12T64Revision 1.1.1
Serial Peripheral Interface (SPI)
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