MC9S12T64 Datasheet, PDF (342/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM8B8C)
PWM Center Align
Enable Register
(PWMCAE)
Address Offset: $00A4
Bit 7
Read:
Write:
CAE7
Reset:
0
6
CAE6
0
5
CAE5
0
4
CAE4
0
3
CAE3
0
2
CAE2
0
1
CAE1
0
Bit 0
CAE0
0
The PWMCAE register contains eight control bits for the selection of
center aligned outputs or left aligned outputs for each PWM channel. If
the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output
will be left aligned. Reference Left Aligned Outputs and Center Aligned
Outputs for a more detailed description of the PWM output modes.
Read: anytime
Write: anytime
CAUTION: Write these bits only when the corresponding channel is disabled.
CAE7 — Center Aligned Output Mode on channel 7
1 = Channel 7 operates in Center Aligned Output Mode.
0 = Channel 7 operates in Left Aligned Output Mode.
CAE6 — Center Aligned Output Mode on channel 6
1 = Channel 6 operates in Center Aligned Output Mode.
0 = Channel 6 operates in Left Aligned Output Mode.
CAE5 — Center Aligned Output Mode on channel 5
1 = Channel 5 operates in Center Aligned Output Mode.
0 = Channel 5 operates in Left Aligned Output Mode.
CAE4 — Center Aligned Output Mode on channel 4
1 = Channel 4 operates in Center Aligned Output Mode.
0 = Channel 4 operates in Left Aligned Output Mode.
CAE3 — Center Aligned Output Mode on channel 3
1 = Channel 3 operates in Center Aligned Output Mode.
0 = Channel 3 operates in Left Aligned Output Mode.
MC9S12T64Revision 1.1.1
Pulse Width Modulator (PWM8B8C)
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