MC9S12T64 Datasheet, PDF (265/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Port Integration Module (PIM)
Register Descriptions
Port P Data
Direction Register
(DDRP)
Address Offset: $00F2
Bit 7
Read:
DDRP7
Write:
Reset: 0
6
5
4
DDRP6 DDRP5 DDRP4
0
0
0
= Reserved or unimplemented
3
DDRP3
0
2
DDRP2
0
1
DDRP1
0
Bit 0
DDRP0
0
Read: Anytime.
Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel is enabled this register has no effect on
the pins.
The PWM forces the I/O state to be an output for each port line
associated with an enabled PWM7–0 channel. Channel 7 can force the
pin to input if the shutdown feature is enabled.
The DDRP bits revert to controlling the I/O direction of a pin when the
associated PWM channel is disabled.
DDRP[7:0] — Data Direction Port P
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus cycles
until the correct value is read on PTP or PTIP registers, when changing
the DDRP register.
Port Integration Module (PIM)
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MC9S12T64Revision 1.1.1