MC9S12T64 Datasheet, PDF (525/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
Register Descriptions
1 = BDM enabled
0 = BDM disabled
NOTE:
ENBDM is set by the firmware immediately out of reset in special
single-chip mode. In secured mode this bit will not be set by the firmware
until after the FLASH erase verify test is complete.
BDMACT — BDM active status
This bit becomes set upon entering BDM. The standard BDM
firmware lookup table is then enabled and put into the memory map.
BDMACT is cleared by a carefully timed store instruction in the
standard BDM firmware as part of the exit sequence to return to user
code and remove the BDM memory from the map.
1 = BDM active
0 = BDM not active
ENTAG — Tagging enable
This bit indicates whether instruction tagging in enabled or disabled.
It is set when the TAGGO command is executed and cleared when
BDM is entered. The serial system is disabled and the tag function
enabled 16 cycles after this bit is written. BDM cannot process serial
commands while tagging is active.
1 = Tagging enabled
0 = Tagging not enabled, or BDM active
SDV — Shift data valid
This bit is set and cleared by the BDM hardware. It is set after data
has been transmitted as part of a firmware read command or after
data has been received as part of a firmware write command. It is
cleared when the next BDM command has been received or
background debug mode is exited. SDV is used by the standard BDM
firmware to control program flow execution.
1 = Data phase of command is complete
0 = Data phase of command not complete
Fast Background Debug Module (FBDM)
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MC9S12T64Revision 1.1.1