MC9S12T64 Datasheet, PDF (33/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Programming Model
The C bit is set when a carry occurs during addition or a borrow
occurs during subtraction. The C bit also acts as an error flag for
multiply and divide operations. Shift and rotate instructions operate
through the C bit to facilitate multiple-word shifts.
1 = Carry or borrow
0 = No carry or borrow
HCS12 CPU registers are an integral part of the CPU and are not
addressed as if they were memory locations.
7
A
15
15
15
15
15
07
B
0 8-BIT ACCUMULATORS A AND B
D
0 16-BIT DOUBLE ACCUMULATOR D (A : B)
X
0 INDEX REGISTER X
Y
0 INDEX REGISTER Y
SP
0 STACK POINTER
PC
0 PROGRAM COUNTER
S X H I N Z V C CONDITION CODE REGISTER
CARRY
OVERFLOW
ZERO
NEGATIVE
IRQ INTERRUPT MASK (DISABLE)
HALF-CARRY FOR BCD ARITHMETIC
XIRQ INTERRUPT MASK (DISABLE)
STOP DISABLE (IGNORE STOP INSTRUCTION)
Figure 10 Programming Model
Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1