MC9S12T64 Datasheet, PDF (30/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
The status bits reflect the results of CPU operations. The five status bits
are half-carry (H), negative (N), zero (Z), overflow (V), and carry/borrow
(C). The half-carry bit is used only for BCD arithmetic operations. The N,
Z, V, and C status bits allow for branching based on the results of a CPU
operation.
Most instructions automatically update condition codes, so it is rarely
necessary to execute extra instructions to load and test a variable. The
condition codes affected by each instruction are shown in the HCS12
CORE User Guide.
The following paragraphs describe common uses of the condition codes.
There are other, more specialized uses. For instance, the C status bit is
used to enable weighted fuzzy logic rule evaluation. Specialized usages
are described in the relevant portions of this guide and in the HCS12
CORE User Guide.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
S
X
H
I
N
Z
V
C
Write:
Reset: 1
1
0
1
0
0
0
0
Figure 9 Condition Code Register (CCR)
S — STOP Mask Bit
Clearing the S bit enables the STOP instruction. Execution of a STOP
instruction causes the on-chip oscillator to stop. This may be
undesirable in some applications. When the S bit is set, the CPU
treats the STOP instruction as a no-operation (NOP) instruction and
continues on to the next instruction. Reset sets the S bit.
1 = STOP instruction disabled
0 = STOP instruction enabled
X — XIRQ Mask Bit
Clearing the X bit enables interrupt requests on the XIRQ pin. The
XIRQ input is an updated version of the nonmaskable interrupt (NMI)
input found on earlier generations of Motorola microcontroller units
MC9S12T64Revision 1.1.1
Central Processing Unit (CPU)
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