MC9S12T64 Datasheet, PDF (392/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
PAMOD — Pulse Accumulator Mode
This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1).
1 = gated time accumulation mode
0 = event counter mode
PEDGE — Pulse Accumulator Edge Control
This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1).
For PAMOD bit = 0 (event counter mode).
1 = rising edges on PT7 pin cause the count to be incremented
0 = falling edges on PT7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
1 = PT7 input pin low enables bus clock divided by 64 clock to
Pulse Accumulator and the trailing rising edge on PT7 sets the
PAIF flag
0 = PT7 input pin high enables bus clock divided by 64 clock to
Pulse Accumulator and the trailing falling edge on PT7 sets the
PAIF flag.
Table 68 Pin Action
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Pin Action
Falling edge
Rising edge
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64
since the ÷64 clock is generated by the timer prescaler.
CLK1, CLK0 — Clock Select Bits
Table 69 Clock Selection
CLK1
0
0
1
1
CLK0
0
1
0
1
Clock Source
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
For the description of PACLK please refer to Figure 72 in page 412.
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
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