MC9S12T64 Datasheet, PDF (285/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Register Descriptions
Lower oscillator amplitude exhibits lower power consumption but could
have adverse effects during any Electro-Magnetic Susceptibility (EMS)
tests.
SYSWAI — System clocks stop in WAIT Mode Bit
Write: anytime
This bit controls the bus clock during Wait Mode.
1 = In Wait Mode, the system clocks stop.
0 = In Wait Mode, the system clocks continue to run.
NOTE: RTI and COP are not affected by SYSWAI bit.
ROAWAI — Reduced Oscillator Amplitude in WAIT Mode Bit
Write: anytime
This bit controls oscillator amplitude during Wait Mode.
1 = Reduced oscillator amplitude in Wait Mode.
0 = Normal oscillator amplitude in Wait Mode.
NOTE:
Lower oscillator amplitude exhibit lower power consumption but could
have adverse effects during any Electro-Magnetic Susceptibility (EMS)
tests.
PLLWAI — PLL stops in WAIT Mode Bit
Write: anytime
If PLLWAI is set, the CRG will clear the PLLSEL bit before entering
Wait Mode. The PLLON bit remains set during Wait Mode but the PLL
is powered down. Upon exiting Wait Mode, the PLLSEL bit has to be
set manually if PLL clock is required.
While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow
the PLL to automatically lock on the selected target frequency after
exiting Wait Mode.
1 = PLL stops in Wait Mode.
0 = PLL keeps running in Wait Mode.
CWAI — Core stops in WAIT Mode Bit
Write: anytime
This bit controls the core clock in Wait Mode.
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1