MC9S12T64 Datasheet, PDF (300/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
The peripheral modules use the Bus Clock. Some peripheral modules
also use the Oscillator Clock. The memory blocks use the Bus Clock. If
the MCU enters Self Clock Mode (see Self Clock Mode in page 305)
Oscillator clock source is switched to PLLCLK running at its minimum
frequency f_SCM. The Bus Clock is used to generate the clock visible at
the ECLK pin. The Core Clock signal is the clock for the HCS12 core.The
Core Clock is twice the Bus Clock as shown in Figure 48. But note that
a CPU cycle corresponds to one Bus Clock.
PLL clock mode is selected with PLLSEL bit in the CLKSEL register.
When selected, the PLL output clock drives SYSCLK for the main
system including the CPU and peripherals. The PLL cannot be turned off
by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is
changed, it takes a maximum of 4 OSCCLK plus 4 PLLCLK cycles to
make the transition. During the transition, all clocks freeze and CPU
activity ceases.
CORE CLOCK:
BUS CLOCK / ECLK
Figure 48 Core Clock and Bus Clock relationship
Clock Monitor
(CM)
The clock monitor circuit is based on an internal resistor-capacitor (RC)
time delay so that it can operate without any MCU clocks. If no OSCCLK
edges are detected within this RC time delay, the clock monitor indicates
failure which asserts self clock mode or generates a system reset
depending on the state of SCME bit in the PLLCTL register (page 286).
If the SCME bit is cleared, CRG generates a Clock Monitor Reset;
otherwise, it enters Self Clock Mode. If the clock monitor is disabled or
the presence of clocks is detected no failure is indicated.The clock
monitor function is enabled/disabled by the CME control bit.
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
For More Information On This Product,
Go to: www.freescale.com