MC9S12T64 Datasheet, PDF (280/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Register
Name
Reserved for
Factory Test
Bit 7
Read:
Write:
6
5
4
3
2
1
Reads to this register return unpredictable values
Bit 0
Address
offset
$003E
Read: 0
0
0
0
0
0
0
0
ARMCOP
$003F
Write: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
= Reserved or unimplemented
Figure 45 CRG Register Map (Continued)
NOTE: Register Address = Base Address (INITRG) + Address Offset
Register Descriptions
NOTE: All bits of all registers in this module are completely synchronous to
internal clocks during a register read.
CRG Synthesizer
Register (SYNR)
NOTE:
The SYNR register controls the multiplication factor of the PLL. If the
PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the PLLCLK from the reference frequency by 2 x
(SYNR+1). PLLCLK will not be below the minimum VCO frequency
(f_SCM).
ėēēĊēĒ = ùĿĖĚĊĊēĒĿ₍--⁽-_ę--^Ě-_Č--^Ä --_č-^ĕ--_ċ--^ę-_ĝ---+--+---^ø--_ø-⁾--₎-
If PLL is selected (PLLSEL=1)PLLCLK, Bus Clock =PLLCLK/2. Bus
Clock must not exceed the maximum operating system frequency
.
Address Offset: $0034
Bit 7
Read:
0
Write:
Reset:
0
6
5
4
0
SYN5
SYN4
0
0
0
= Unimplemented or reserved
3
SYN3
0
2
SYN2
0
1
SYN1
0
0
SYN0
0
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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