MC9S12T64 Datasheet, PDF (223/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Flash EEPROM 64K
Functional Description
Program and
Erase Sequence in
Normal Mode
A Command State Machine is used to supervise the write sequencing for
program and erase. The erase-verify command follows the same flow.
Before starting a command sequence, it is necessary to verify that there
is no pending access error or protection violation (the ACCERR and
PVIOL flags should be cleared in the FSTAT register). It is then required
to set the PPAGE register when in special modes. The procedure is as
follows:
1. Verify that all ACCERR and PVIOL flags in the FSTAT register are
cleared in all banks. This requires to check the FSTAT content for
all combinations of the BKSEL bit in the FCNFG register.
2. Write to bit BKSEL in the FCNFG register to select the bank of
registers corresponding to the 32K flash block to be programmed
or erased (i.e. Flash 0 or 1). See Figure 23, 24 for further details.
3. In special modes, write to the core PPAGE register ($x030) to
select one of the 16K pages to be programmed if programming in
the $8000–$BFFF address range. There is no need to set PPAGE
when programming in the $4000-$7FFF or $C000-$FFFF address
ranges or when operating in normal modes.
After this possible initialization step the CBEIF flag should be tested to
ensure that the address, data and command buffers are empty. If so, the
program/erase command write sequence can be started. The following
3-step command write sequence must be strictly adhered to and no
intermediate writes to the Flash module are permitted between the 3
steps. It is possible to read any Flash register during a command
sequence. The command sequence is as follows:
1. Write the aligned data word (16-bits) to be programmed to the
valid Flash address space between $0000 and $FFFF. The
address and data will be stored in internal buffers. For program, all
address bits are valid. For erase, the value of the data bytes is
don’t care. For mass erase the address can be anywhere in the
available address space of the 32K byte block to be erased. For
sector erase the address bits 8:0 are ignored for the Flash.
2. Write the program or erase command to the command buffer.
These commands are listed in Table 45.
3. Clear the CBEIF flag by writing a “1” to it to launch the command.
When the CBEIF flag is cleared, the CCIF flag is cleared by
hardware indicating that the command was successfully
launched. The ACCERR and PVIOL flags should be tested to
Flash EEPROM 64K
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MC9S12T64Revision 1.1.1