MC9S12T64 Datasheet, PDF (463/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Register Descriptions
1 = Master mode
0 = Slave mode
CPOL — SPI Clock Polarity Bit
This bit selects an inverted or non-inverted SPI clock. To transmit
data between SPI modules, the SPI modules must have identical
CPOL values.
1 = Active-low clocks selected; SCK idles high
0 = Active-high clocks selected; SCK idles low
CPHA — SPI Clock Phase Bit
This bit is used to shift the SCK serial clock.
1 = The first SCK edge is issued at the beginning of the 8-cycle
transfer operation
0 = The first SCK edge is issued one-half cycle into the 8-cycle
transfer operation
SSOE — Slave Select Output Enable
The SS output feature is enabled only in the master mode by
asserting the SSOE as shown in Table 81.
Table 81 SS Input / Output Selection
MOD
FEN
SSOE
Master Mode
Slave Mode
0
0
SS not used by SPI
SS input
0
1
SS not used by SPI
SS input
1
0 SS input with MODF feature SS input
1
1
SS output
SS input
LSBFE — SPI LSB-First Enable
This bit does not affect the position of the msb and lsb in the data
register. Reads and writes of the data register always have the msb
in bit 7.
1 = Data is transferred least significant bit first.
0 = Data is transferred most significant bit first.
Serial Peripheral Interface (SPI)
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MC9S12T64Revision 1.1.1