MC9S12T64 Datasheet, PDF (387/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
Timer Interrupt
Enable Register
(TIE)
Register offset: $004C
Bit 7
Read:
C7I
Write:
Reset:
0
6
5
4
3
2
1
Bit 0
C6I
C5I
C4I
C3I
C2I
C1I
C0I
0
0
0
0
0
0
0
Read or write anytime.
The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status
register. If cleared, the corresponding flag is disabled from causing a
hardware interrupt. If set, the corresponding flag is enabled to cause a
interrupt.
C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable
Timer System
Control Register 2
(TSCR2)
Register offset: $004D
Bit 7
Read:
TOI
Write:
Reset:
0
6
5
4
0
0
0
0
0
0
= Reserved or unimplemented
3
2
1
Bit 0
TCRE
PR2
PR1
PR0
0
0
0
0
Read or write anytime.
TOI — Timer Overflow Interrupt Enable
1 = Hardware interrupt requested when TOF flag set
0 = Interrupt inhibited
TCRE — Timer Counter Reset Enable
This bit allows the timer counter to be reset by a successful output
compare 7 event. This mode of operation is similar to an up-counting
modulus counter.
Enhanced Capture Timer (ECT)
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MC9S12T64Revision 1.1.1