MC9S12T64 Datasheet, PDF (321/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Reset Description
Computer
Operating
Properly
Watchdog (COP)
Reset
When COP is enabled, the CRG expects sequential write of $55 and
$AA (in this order) to the ARMCOP register during the selected time-out
period. Once this is done, the COP time-out period restarts. If the
program fails to do this the CRG will generate a reset. Also, if any value
other than $55 or $AA is written, the CRG immediately generates a
reset. In case window COP operation is enabled writes ($55 or $AA) to
the ARMCOP register must occur in the last 25% of the selected
time-out period. A premature write the CRG will immediately generate a
reset.
As soon as the reset sequence is completed the reset generator checks
the reset condition. If no clock monitor failure is indicated and the latched
state of the COP timeout is true, processing begins by fetching the COP
vector.
Low Voltage
Detection Reset
The CRG generates a Low Voltage Detection Reset in case all of the
following conditions are true:
• VDDR voltage falls to V_LVR level and remains at or below that level
for 17 or more consecutive bus clock cycles.
• The LVD reset enable bit (LVDRE) in the LVDCR register is set.
As showed in Figure 50, after a LVD reset occurs, the CRG will perform
a maximum of 50 check windows before entering Self Clock Mode and
executing the reset sequence. If OSCCLK is considered valid before 50
check windows are complete, the clock quality check is successfully
terminated and reset sequence is executed. More details about the LVD
module can be found in the section in page 185.
Power-On Reset
The on-chip voltage regulator detects when VDD to the MCU has
reached a certain level and asserts power on reset. As soon as a power
on reset is triggered the CRG performs a quality check on the incoming
clock signal. As soon as clock quality check indicates a valid Oscillator
Clock signal the reset sequence starts using the Oscillator clock. If after
50 check windows the clock quality check indicated a non-valid
Oscillator Clock the reset sequence starts using Self-Clock Mode. See
Figure 50.
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1