MC9S12T64 Datasheet, PDF (579/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Electrical Characteristics
Reset, Oscillator and PLL Characteristics
reset vector without doing a clock quality check, if there was an
oscillation before reset.
Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A
clock quality check as after POR is performed before releasing the
clocks to the system.
Pseudo Stop and
Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same
since the oscillator was not stopped in both modes. The controller can
be woken up by internal or external interrupts. After t_wrs the CPU starts
fetching the interrupt vector.
Oscillator
The device features internal Colpitts and Pierce oscillators. By asserting
the XCLKS input during reset the Colpitts oscillator can be bypassed
allowing the input of a square wave or the Pierce oscillator. Before
asserting the oscillator to the internal system clocks the quality of the
oscillation is checked for each start from either power-on, LVD reset,
STOP or oscillator fail. t_CQOUT specifies the maximum time before
switching to the internal self clock mode after POR/LVDR or STOP if a
proper oscillation is not detected. The fastest startup time possible is
given by n_uposc. The quality check also determines the minimum
oscillator start-up time t_UPOSC. The device also features a clock monitor.
A Clock Monitor Failure is asserted if the frequency of the incoming clock
signal is below the Clock Monitor Failure Assert Frequency f_CMFA.
Electrical Characteristics
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MC9S12T64Revision 1.1.1