MC9S12T64 Datasheet, PDF (291/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Register Descriptions
CRG COP Control This register controls the COP (Computer Operating Properly)
Register (COPCTL) watchdog.
Address Offset: $003C
Bit 7
6
5
4
3
2
1
0
Read:
0
0
0
WCOP
RSBCK
CR2
CR1
CR0
Write:
Reset:
0
1
0
0
0
0
1
1
Read: anytime.
Write: once
WCOP — Window COP mode Bit
When set, a write to the ARMCOP register must occur in the last 25%
of the selected period. A write during the first 75% of the selected
period will reset the part. As long as all writes occur during this
window, $55 can be written as often as desired. Once $AA is written
after the $55, the time-out logic restarts and the user must wait until
the next window before writing to ARMCOP. Table 52 shows the
exact duration of this window for the seven available COP rates.
1 = Window COP operation
0 = Normal COP operation
RSBCK — COP and RTI stop in Active BDM Bit
1 = Stops the COP and RTI counters whenever the part is in Active
background debug mode.
0 = Allows the COP and RTI to keep running in Active background
debug mode.
CR[2:0] — COP Watchdog Timer Rate select
These bits select the COP time-out rate (see Table 52). The COP
time-out period is OSCCLK period divided by CR[2:0] value. Writing
a nonzero value to CR[2:0] enables the COP counter and starts the
time-out period. A COP counter time-out causes a system reset. This
can be avoided by periodically (before time-out) re-initializing the
COP counter via the ARMCOP register.
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1