MC9S12T64 Datasheet, PDF (395/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
NOTE: When clocking pulse and write to the registers occurs simultaneously,
write takes priority and the register is not incremented.
Pulse
Accumulators
Count Registers
(PACN1, PACN0)
Register offset: $0064–$0065
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
0
0
0
0
0
0
0
0
Read or write any time.
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator. When PACB is enabled, (PBEN=1
in PBCTL) the PACN1 and PACN0 registers contents are respectively
the high and low byte of the PACB.
When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in
PBFLG (see page 405) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
NOTE:
The input capture edge circuits of 8-bit pulse accumulators are
configured with control bits EDGnA EDGnB in the TCTL4 register (see
page 386).
NOTE: When clocking pulse and write to the registers occurs simultaneously,
write takes priority and the register is not incremented.
Enhanced Capture Timer (ECT)
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MC9S12T64Revision 1.1.1