MC9S12T64 Datasheet, PDF (477/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Functional Description
Transfer
Begin
End
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
t_L
MSB first (LSBFE = 0): MSB
LSB first (LSBFE = 1): LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
t_L = Minimum leading time before the first SCK edge
t_T = Minimum trailing time after the last SCK edge
t_I = Minimum idling time between transfers (minimum SS high time)
t_L, t_T, and t_I are guaranteed for the master mode and required for the slave mode.
Bit 1
Bit 6
t_T t_I t_L
LSB Minimum 1/2 SCK
MSB
for t_T, t_l, t_L
Figure 94 SPI Clock Format 0 (CPHA = 0)
The SS line should be deasserted at least for minimum idle time (half
SCK cycle) between the successive transfers (SS should not be tied low
all the times in this mode). If SS is not deasserted between the
successive transmission then the new byte written to the data register
would not be transmitted, instead the last received byte would be
transmitted.
CPHA = 1 Transfer
Format
Some peripherals require the first SCK edge before the first data bit
becomes available at the data out pin; the second edge clocks data into
the system. In this format, the first SCK edge is issued by setting the
CPHA bit at the beginning of the 8-cycle transfer operation.
Serial Peripheral Interface (SPI)
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MC9S12T64Revision 1.1.1