MC9S12T64 Datasheet, PDF (480/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
The SPI clock rate is determined by the product of the value in the baud
rate preselection bits (SPPR2–SPPR0) and the value in the baud rate
selection bits (SPR2–SPR0). The bus clock divisor equation is shown in
Figure 96.
When all bits are clear (the default condition), the bus clock is divided by
2. When the selection bits (SPR2–SPR0) are 001 and the preselection
bits (SPPR2–SPPR0) are 000, the bus clock divisor becomes 4. When
the selection bits are 010, the bus clock divisor becomes 8, etc.
When the preselection bits are 001, the divisor determined by the
selection bits is multiplied by 2. When the preselection bits are 010, the
divisor is multiplied by 3, etc. See Table 83 for baud rate calculations for
all bit conditions, based on a 16 MHz bus clock.The two sets of selects
allows the clock to be divided by a non-power of two to achieve other
baud rates such as divide by 6, divide by 10, etc.
The baud rate generator is activated only when the SPI is in the master
mode and a serial transfer is taking place. In the other cases, the divider
is disabled to decrease I_DD current.
ĉļĺĊijĶĪIJċİĽİĺĶĹ = (Ěėėę + ø) • ù^{(Ěėę + ø)}
Figure 96 Bus Clock Divisor Equation
Special Features
SS Output
The SS output feature automatically drives the SS pin low during
transmission to select external devices and drives it high during idle to
deselect external devices. When SS output is selected, the SS output
pin is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI
operation by asserting SSOE and MODFEN bit as shown in Table 81.
The mode fault feature is disabled while SS output is enabled.
MC9S12T64Revision 1.1.1
Serial Peripheral Interface (SPI)
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