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MC9S12T64 Datasheet, PDF (31/608 Pages) Motorola, Inc – Specification
Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Programming Model
(MCUs). Nonmaskable interrupts are typically used to deal with major
system failures such as loss of power. However, enabling
nonmaskable interrupts before a system is fully powered and
initialized can lead to spurious interrupts. The X bit provides a
mechanism for masking nonmaskable interrupts until the system is
stable.
Reset sets the X bit. As long as the X bit remains set, interrupt service
requests made via the XIRQ pin are not recognized. Software must
clear the X bit to enable interrupt service requests from the XIRQ pin.
Once software clears the X bit, enabling XIRQ interrupt requests, only
a reset can set it again. The X bit does not affect I bit maskable
interrupt requests.
When the X bit is clear and an XIRQ interrupt request occurs, the CPU
stacks the cleared X bit. It then automatically sets the X and I bits in
the CCR to disable XIRQ and maskable interrupt requests during the
XIRQ interrupt service routine.
An RTI instruction at the end of the interrupt service routine restores
the cleared X bit to the CCR, re-enabling XIRQ interrupt requests.
1 = XIRQ interrupt requests disabled
0 = XIRQ interrupt requests enabled
H — Half-Carry Bit
The H bit indicates a carry from bit 3 of the result during an addition
operation. The DAA instruction uses the value of the H bit to adjust
the result in accumulator A to BCD format. ABA, ADD, and ADC are
the only instructions that update the H bit.
1 = Carry from bit 3 after ABA, ADD, or ADC instruction
0 = No carry from bit 3 after ABA, ADD, or ADC instruction
I — Interrupt Mask Bit
Clearing the I bit enables maskable interrupt sources. Reset sets the
I bit. To enable maskable interrupt requests, software must clear the
I bit. Maskable interrupt requests that occur while the I bit is set
remain pending until the I bit is cleared.
Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1