MC9S12T64 Datasheet, PDF (150/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Port B Data
Direction Register
(DDRB)
Address Offset: $0003
Bit 7
Read:
BIT 7
Write:
Reset:
0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
BIT 0
0
0
0
0
0
0
0
Read and write: anytime (provided this register is in the map).
This register controls the data direction for Port B. When Port B is
operating as a general purpose I/O port, DDRB determines the
primary direction for each Port B pin. A “1” causes the associated port
pin to be an output and a “0” causes the associated pin to be a
high-impedance input. The value in a DDR bit also affects the source
of data for reads of the corresponding PORTB register. If the DDR bit
is zero (input) the buffered pin input is read. If the DDR bit is one
(output) the associated port data register bit state is read.
This register is not in the on-chip map in expanded and peripheral
modes. It is reset to $00 so the DDR does not override the three-state
control signals.
DDRB7–0 — Data Direction Port B
1 = Configure the corresponding I/O pin as an output
0 = Configure the corresponding I/O pin as an input
MC9S12T64Revision 1.1.1
Multiplexed External Bus Interface (MEBI)
For More Information On This Product,
Go to: www.freescale.com