MC9S12T64 Datasheet, PDF (57/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Instruction Set Overview
Table 10 Access Detail Notation (Continued)
U Unstack 16-bit data. A U cycle is extended to two bus cycles if the MCU is operating with an 8-bit
external data bus and the SP is pointing to external memory. There can be additional stretching
when the address space is assigned to a chip-select circuit programmed for slow memory. A U cycle
is also stretched if it corresponds to a misaligned access to a memory that is not designed for
single-cycle misaligned access. The internal RAM is designed to allow single-cycle misaligned word
access.
V 16-bit vector fetch. Vectors are always aligned 16-bit words. A V cycle is extended to two bus cycles
if the MCU is operating with an 8-bit external data bus and the program is stored in external memory.
There can be additional stretching when the address space is assigned to a chip-select circuit
programmed for slow memory.
t 8-bit conditional read. A t cycle is either a data read cycle or a free cycle, depending on the data and
flow of the REVW instruction. A t cycle is stretched only when controlled by a chip-select circuit
programmed for slow memory.
T 16-bit conditional read. A T cycle is either a data read cycle or a free cycle, depending on the data
and flow of the REV or REVW instruction. A T cycle is extended to two bus cycles if the MCU is
operating with an 8-bit external data bus and the corresponding data is stored in external memory.
There can be additional stretching when the address space is assigned to a chip-select circuit
programmed for slow memory. A T cycle is also stretched if it corresponds to a misaligned access to
a memory that is not designed for single-cycle misaligned access.
x 8-bit conditional write. An x cycle is either a data write cycle or a free cycle, depending on the data
and flow of the REV or REVW instruction. An x cycle is stretched only when controlled by a
chip-select circuit programmed for slow memory.
Special Notation for Branch Taken/Not Taken
PPP/P A short branch requires three cycles if taken, one cycle if not taken. Since the instruction consists of
a single word containing both an opcode and an 8-bit offset, the not-taken case is simple — the
queue advances, another program word fetch is made, and execution continues with the next
instruction. The taken case requires that the queue be refilled so that execution can continue at a
new address. First, the effective address of the destination is determined, then the CPU performs
three program word fetches from that address.
OPPP/OPO A long branch requires four cycles if taken, three cycles if not taken. An O cycle is required because
all long branches are page two opcodes and thus include the $18 prebyte. The prebyte is treated as
a one-byte instruction. If the prebyte is misaligned, the O cycle is a P cycle; if the prebyte is aligned,
the O cycle is an f cycle. As a result, both the taken and not-taken cases use one O cycle for the
prebyte. In the not-taken case, the queue must advance so that execution can continue with the next
instruction, and another O cycle is required to maintain the queue. The taken case requires that the
queue be refilled so that execution can continue at a new address. First, the effective address of the
destination is determined, then the CPU performs three program word fetches from that address.
Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1