MC9S12T64 Datasheet, PDF (50/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Table 4 Instruction Set Summary (Continued)
Source Form
TBEQ abdxysp,rel9
TBL oprx0_xysppc
TBNE abdxysp,rel9
TFR abcdxysp,abcdxysp
TPASame as TFR CCR,A
Operation
Test and branch if equal to 0
If (counter)=0, then (PC)+2+rel⇒PC
Table lookup and interpolate, 8-bit
(M)+[(B)×((M+1)–(M))]⇒A
Test and branch if not equal to 0
If (counter)≠0, then (PC)+2+rel⇒PC
Transfer from register to register
(r1)⇒r2r1 and r2 same size
$00:(r1)⇒r2r1=8-bit; r2=16-bit
(r1_L)⇒r2r1=16-bit; r2=8-bit
Transfer CCR to A; (CCR)⇒A
Address
Machine
Mode Coding (Hex)
REL
(9-bit)
04 lb rr
IDX
18 3D xb
REL
(9-bit)
INH
04 lb rr
B7 eb
INH
B7 20
Access Detail
PPP (branch)
PPO (no branch)
ORfffP
PPP (branch)
PPO (no branch)
P
P
SXHINZVC
––––––––
––––∆∆–∆
––––––––
––––––––
or
∆⇓∆∆∆∆∆∆
––––––––
TRAP trapnum
TST opr16a
TST oprx0_xysppc
TST oprx9,xysppc
TST oprx16,xysppc
TST [D,xysppc]
TST [oprx16,xysppc]
TSTA
TSTB
TSXSame as TFR SP,X
Trap unimplemented opcode;
(SP)–2⇒SP
RTN_H:RTN_L⇒M_SP:M_SP+1
(SP)–2⇒SP; (Y_H:Y_L)⇒M_SP:M_SP+1
(SP)–2⇒SP; (X_H:X_L)⇒M_SP:M_SP+1
(SP)–2⇒SP; (B:A)⇒M_SP:M_SP+1
(SP)–1⇒SP; (CCR)⇒M_SP
1⇒I; (trap vector)⇒PC
Test M; (M)–0
Test A; (A)–0
Test B; (B)–0
Transfer SP to X; (SP)⇒X
INH
18 tn
tn = $30–$39
or
tn = $40–$FF
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
INH
F7 hh ll
E7 xb
E7 xb ff
E7 xb ee ff
E7 xb
E7 xb ee ff
97
D7
B7 75
OVSPSSPSsP
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
O
O
P
–––1––––
––––∆∆00
––––––––
TSYSame as TFR SP,Y
Transfer SP to Y; (SP)⇒Y
INH
B7 76
P
––––––––
TXSSame as TFR X,SP
Transfer X to SP; (X)⇒SP
INH
B7 57
P
––––––––
TYSSame as TFR Y,SP
Transfer Y to SP; (Y)⇒SP
INH
B7 67
P
––––––––
WAI
Wait for interrupt; (SP)–2⇒SP
INH
3E
OSSSSsf
––––––––
RTN_H:RTN_L⇒M_SP:M_SP+1
(before interrupt)
or
(SP)–2⇒SP; (Y_H:Y_L)⇒M_SP:M_SP+1
(SP)–2⇒SP; (X_H:X_L)⇒M_SP:M_SP+1
fVfPPP
(after interrupt)
–––1––––
or
(SP)–2⇒SP; (B:A)⇒M_SP:M_SP+1
–1–1––––
(SP)–1⇒SP; (CCR)⇒M_SP
WAV
B
∑ ^Si^Fi ^{⇒ Y:D}
i=1
B
∑ ^Fi ^{⇒ X}
i=1
Calculate
weighted
average; sum of
products (SOP)
and sum of
weights (SOW)*
Special
18 3C
Of(frr^ffff)O** _{– – ? – ? ∆ ? ?}
SSS+UUUrr^***
*Initialize B, X, and Y: B=number of elements; X points at first element in S_i list; Y points at first element in F_i list. All S_i and F_i elements are 8-bit values.
**The frr^ffff sequence is the loop for one iteration of SOP and SOW accumulation. The ^ denotes a check for pending interrupt requests.
***Additional cycles caused by an interrupt: SSS is the exit sequence and UUUrr^ is the re-entry sequence. Intermediate values use six stack bytes.
wavr*
Resume executing interrupted WAV Special 3C
UUUrr^ffff(frr^ _{– – ? – ? ∆ ? ?}
ffff)O**
SSS+UUUrr^***
MC9S12T64Revision 1.1.1
Central Processing Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com