MC9S12T64 Datasheet, PDF (40/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Source Form
CLR opr16a
CLR oprx0_xysppc
CLR oprx9,xysppc
CLR oprx16,xysppc
CLR [D,xysppc]
CLR [oprx16,xysppc]
CLRA
CLRB
CLVSame as ANDCC #$FD
CMPA #opr8i
CMPA opr8a
CMPA opr16a
CMPA oprx0_xysppc
CMPA oprx9,xysppc
CMPA oprx16,xysppc
CMPA [D,xysppc]
CMPA [oprx16,xysppc]
CMPB #opr8i
CMPB opr8a
CMPB opr16a
CMPB oprx0_xysppc
CMPB oprx9,xysppc
CMPB oprx16,xysppc
CMPB [D,xysppc]
CMPB [oprx16,xysppc]
COM opr16a
COM oprx0_xysppc
COM oprx9,xysppc
COM oprx16,xysppc
COM [D,xysppc]
COM [oprx16,xysppc]
COMA
COMB
CPD #opr16i
CPD opr8a
CPD opr16a
CPD oprx0_xysppc
CPD oprx9,xysppc
CPD oprx16,xysppc
CPD [D,xysppc]
CPD [oprx16,xysppc]
CPS #opr16i
CPS opr8a
CPS opr16a
CPS oprx0_xysppc
CPS oprx9,xysppc
CPS oprx16,xysppc
CPS [D,xysppc]
CPS [oprx16,xysppc]
CPX #opr16i
CPX opr8a
CPX opr16a
CPX oprx0_xysppc
CPX oprx9,xysppc
CPX oprx16,xysppc
CPX [D,xysppc]
CPX [oprx16,xysppc]
Table 4 Instruction Set Summary (Continued)
Operation
Clear M; $00⇒M
Clear A; $00⇒A
Clear B; $00⇒B
Clear V
Compare A
(A)–(M) or (A)–imm
Compare B
(B)–(M) or (B)–imm
Complement M; (M)=$FF–(M)⇒M
Complement A; (A)=$FF–(A)⇒A
Complement B; (B)=$FF–(B)⇒B
Compare D
(A:B)–(M:M+1)
or (A:B)–imm
Compare SP
(SP)–(M:M+1)
or (SP)–imm
Compare X
(X)–(M:M+1)
or (X)–imm
Address
Machine
Mode Coding (Hex)
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
79 hh ll
69 xb
69 xb ff
69 xb ee ff
69 xb
69 xb ee ff
87
C7
IMM
10 FD
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
81 ii
91 dd
B1 hh ll
A1 xb
A1 xb ff
A1 xb ee ff
A1 xb
A1 xb ee ff
C1 ii
D1 dd
F1 hh ll
E1 xb
E1 xb ff
E1 xb ee ff
E1 xb
E1 xb ee ff
71 hh ll
61 xb
61 xb ff
61 xb ee ff
61 xb
61 xb ee ff
41
51
8C jj kk
9C dd
BC hh ll
AC xb
AC xb ff
AC xb ee ff
AC xb
AC xb ee ff
8F jj kk
9F dd
BF hh ll
AF xb
AF xb ff
AF xb ee ff
AF xb
AF xb ee ff
8E jj kk
9E dd
BE hh ll
AE xb
AE xb ff
AE xb ee ff
AE xb
AE xb ee ff
Access Detail
PwO
Pw
PwO
PwP
PIfw
PIPw
O
O
P
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
SXHINZVC
––––0100
––––––0–
––––∆∆∆∆
––––∆∆∆∆
––––∆∆01
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
MC9S12T64Revision 1.1.1
Central Processing Unit (CPU)
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