MC9S12T64 Datasheet, PDF (51/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Instruction Set Overview
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Machine
Mode Coding (Hex)
Access Detail S X H I N Z V C
*wavr is a pseudoinstruction that recovers intermediate results from the stack rather than initializing them to 0.
**The frr^ffff sequence is the loop for one iteration of SOP and SOW recovery. The ^ denotes a check for pending interrupt requests.
***These are additional cycles caused by an interrupt: SSS is the exit sequence and UUUrr^ is the re-entry sequence.
XGDXSame as EXG D, X
Exchange D with X; (D)⇔(X)
INH
B7 C5
P
––––––––
XGDYSame as EXG D, Y
Exchange D with Y; (D)⇔(Y)
INH
B7 C6
P
––––––––
Register and
Memory Notation
Table 5 Register and Memory Notation
A or a Accumulator A
An Bit n of accumulator A
B or b Accumulator B
Bn Bit n of accumulator B
D or d Accumulator D
Dn Bit n of accumulator D
X or x Index register X
X_H High byte of index register X
X_L Low byte of index register X
Xn Bit n of index register X
Y or y Index register Y
Y_H High byte of index register Y
Y_L Low byte of index register Y
Yn Bit n of index register Y
SP or sp Stack pointer
SPn Bit n of stack pointer
PC or pc Program counter
PC_H High byte of program counter
PC_L Low byte of program counter
CCR or c Condition code register
M Address of 8-bit memory location
Mn Bit n of byte at memory location M
Rn Bit n of the result of an arithmetic or logical operation
In Bit n of the intermediate result of an arithmetic or logical operation
RTN_H High byte of return address
RTN_L Low byte of return address
( ) Contents of
Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1