MC9S12T64 Datasheet, PDF (324/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Interrupts
General
This section describes all interrupts originated by the CRG.
The interrupts/reset vectors requested by the CRG are listed in
Table 59.
Table 59 CRG Interrupt Vectors
Vector Address
$FFF0, $FFF1
$FFC6, $FFC7
$FFC4, $FFC5
Interrupt Source
Real Time interrupt
LOCK interrupt
SCM interrupt
CCR
Mask
I bit
I bit
I bit
Local Enable
CRGINT (RTIE)
CRGINT (LOCKIE)
CRGINT (SCMIE)
Description of
Interrupt
Operation
Real Time Interrupt
The CRG generates a real time interrupt when the selected interrupt
time period elapses. RTI interrupts are locally disabled by setting the
RTIE bit to zero. The real time interrupt flag (RTIF) is set to1 when a
timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during Pseudo Stop Mode if the PRE bit is set
to 1. This feature can be used for periodic wakeup from Pseudo Stop if
the RTI interrupt is enabled.
PLL Lock Interrupt
The CRG generates a PLL Lock interrupt when the LOCK condition of
the PLL has changed, either from a locked state to an unlocked state or
vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit
to zero. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK
condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF
bit.
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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