MC9S12T64 Datasheet, PDF (539/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
Functional Description
Hardware Delay in
SPI Mode
A hardware delay is required between serial transfers when the BDM
needs to access the bus to complete an operation. For example, on a
hardware read a hardware delay is required after the address is sent so
that the data can be accessed before it is returned. On a hardware write,
a hardware delay is required after the write data is sent so that the write
occurs before the next command is sent.
In SPI mode, the hardware delay allows the BDM to synchronize to the
incoming serial data, load up the appropriate registers for the bus
access, synchronize with the CPU to steal the bus, complete the bus
access and for a read, put the read data into the shifter to return it.
The hardware delay takes into account the part of the operation that
occurs between the rising edges of the serial clock. At the fastest
transfer rate this is a total of eight target clocks. At the fastest rate, the
user must wait eight target clocks which is the hardware delay. If
SCKBDM was running slower, at 12 target clocks per bit, the hardware
delay reduces to zero for single chip mode and to 13 for expanded mode
(worst case).
This can be determined with the equations:
• For internal-only accesses
Hardware Delay = 12TC – (SCKBDM PERIOD)
• For external accesses allowing for stretch and wide bus
Hardware Delay = 21TC – (SCKBDM PERIOD)
• For external accesses allowing for stretch and narrow bus
Hardware Delay = 25TC – (SCKBDM PERIOD)
Where: If the hardware delay goes negative, it is zero.
For example, if the SPI is running at 8 target clocks per bit, we get a 4
TC delay for internal accesses, a 13 TC delay for external accesses with
a wide bus and stretch, and a 17 TC delay for external accesses with a
narrow bus and stretch.
BDM Serial
Interface
The BDM module communicates with external devices serially via the
MCU mode control BKGD pin. During reset, this pin is a mode select
input which selects between normal and special modes of operation.
Fast Background Debug Module (FBDM)
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MC9S12T64Revision 1.1.1