MC9S12T64 Datasheet, PDF (470/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
transmitted immediately after the previous transmission has
completed. The SPI Transmitter empty flag in SPISR indicates when
the SPI data register is ready to accept new data.
NOTE: Do not write to the SPI data register unless the SPTEF bit is high.
Reading the data can occur anytime from after the SPIF is set to
before the end of the next transfer. If the SPIF is not serviced by the
end of the successive transfers, those data bytes are lost and the data
within the SPIDR retains the first byte until SPIF is serviced.
NOTE: After reset the content of the SPI Shift Register is undefined until a data
byte is stored into SPIDR.
Functional Description
The SPI module allows a duplex, synchronous, serial communication
between the MCU and peripheral devices. Software can poll the SPI
status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI
control register 1. While SPE is set, the four associated SPI port pins are
dedicated to the SPI function as:
• Slave select (SS)
• Serial clock (SCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO)
The main element of the SPI system is the SPI data register. The 8-bit
data register in the master and the 8-bit data register in the slave are
linked by the MOSI and MISO pins to form a distributed 16-bit register.
When a data transfer operation is performed, this 16-bit register is
serially shifted eight bit positions by the SCK clock from the master; data
is exchanged between the master and the slave. Data written to the
master SPI data register becomes the output data for the slave, and data
read from the master SPI data register after a transfer operation is the
input data from the slave.
MC9S12T64Revision 1.1.1
Serial Peripheral Interface (SPI)
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