MC9S12T64 Datasheet, PDF (25/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit
(CPU)
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Introduction
The HCS12 CPU is a high-speed, 16-bit processing unit. It has full 16-bit
data paths and wider internal registers (up to 20 bits) for high-speed
extended math instructions. The instruction set is a proper superset of
the M68HC11instruction set. The HCS12 CPU allows instructions with
odd byte counts, including many single-byte instructions. This provides
efficient use of ROM space. An instruction pipe buffers program
information so the CPU always has immediate access to at least three
bytes of machine code at the start of every instruction. The HCS12 CPU
also offers an extensive set of indexed addressing capabilities.
Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1