MC9S12T64 Datasheet, PDF (506/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Analog to Digital Converter (ATD)
1 = External trigger overrun error has occurred
0 = No External trigger overrun error has occurred
FIFOR — FIFO Over Run Flag.
This bit indicates that a result register has been written to before its
associated conversion complete flag (CCF) has been cleared. This
flag is most useful when using the FIFO mode because the flag
potentially indicates that result registers are out of sync with the input
channels. However, it is also practical for non-FIFO modes, and
indicates that a result register has been over written before it has
been read (i.e. the old data has been lost). This flag is cleared when
one of the following occurs:
A) Write “1” to FIFOR
B) Write to ATDCTL5 (a new conversion sequence is started)
1 = An over run condition exists
0 = No over run has occurred
CC2/CC1/CC0 — Conversion Counter
These 3 read-only bits are the binary value of the conversion counter.
The conversion counter points to the result register that will receive
the result of the current conversion. E.g. CC2=1, CC1=1, CC0=0
indicates that the result of the current conversion will be in ATD Result
Register 6. If in non-FIFO mode (FIFO=0) the conversion counter is
initialized to zero at the begin and end of the conversion sequence. If
in FIFO mode (FIFO=1) the register counter is not initialized. The
conversion counters wraps around when its maximum value is
reached.
ATD Test Register 1 This register contains the SC bit used to enable special channel
(ATDTEST1)
conversions.
Address Offset: $0089
Bit 7
Read:
Write:
Reset:
0
6
5
4
3
2
Reads to these bits return unpredictable values.
0
0
0
0
0
Unimplemented or Reserved
1
Bit 0
SC
0
0
MC9S12T64Revision 1.1.1
Analog to Digital Converter (ATD)
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