MC9S12T64 Datasheet, PDF (584/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Electrical Characteristics
Table 119 SPI Master Mode Timing Characteristics⁽¹⁾
Conditions are shown in Table 106 unless otherwise noted, CLOAD = 200pF on all outputs
Num
Rating
Symbol
Min
Typ
Max
Unit
1
Operating Frequency
f_op
DC
1/4
f_bus
1
SCK Period t_sck = 1/ f_op
t_sck
4
2048
t_bus
2
Enable Lead Time
t_lead
1/2
—
t_sck
3
Enable Lag Time
t_lag
1/2
t_sck
4
Clock (SCK) High or Low Time
t_wsck
t_bus − 30
1024 t_bus
ns
5
Data Setup Time (Inputs)
t_su
25
ns
6
Data Hold Time (Inputs)
t_hi
0
ns
9
Data Valid (after SCK Edge)
t_v
25
ns
10 Data Hold Time (Outputs)
t_ho
0
ns
11 Rise Time Inputs and Outputs
t_r
25
ns
12 Fall Time Inputs and Outputs
t_f
25
ns
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table 120.
Slave Mode
Figure 114 and Figure 115 illustrate the slave mode timing. Timing
values are shown in Table 120.
MC9S12T64Revision 1.1.1
Electrical Characteristics
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