MC9S12T64 Datasheet, PDF (297/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Functional Description
In tracking mode, the filter makes only small corrections to the
frequency of the VCO. PLL jitter is much lower in tracking mode,
but the response to noise is also slower. The PLL enters tracking
mode when the VCO frequency is nearly correct and the TRACK
bit is set in the CRGFLG register.
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
PLL clock (PLLCLK) is safe to use as the source for the system and core
clocks. If PLL LOCK interrupt requests are enabled, the software can
wait for an interrupt request and then check the LOCK bit. If CPU
interrupts are disabled, software can poll the LOCK bit continuously
(during PLL start-up, usually) or at periodic intervals. In either case, only
when the LOCK bit is set, is the PLLCLK clock safe to use as the source
for the system and core clocks. If the PLL is selected as the source for
the system and core clocks and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate
action, depending on the application.
The following conditions apply when the PLL is in automatic bandwidth
control mode (AUTO=1):
• The TRACK bit is a read-only indicator of the mode of the filter.
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• CPU interrupts can occur if enabled (LOCKIE = 1) when the lock
condition changes, toggling the LOCK bit.
The PLL can also operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below the
maximum system frequency (f_sys) and require fast start-up. The
following conditions apply when in manual mode:
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1