MC9S12T64 Datasheet, PDF (295/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Functional Description
Phase Locked
Loop (PLL)
The PLL is used to run the MCU from a different time base than the
incoming OSCCLK. For increased flexibility, OSCCLK can be divided in
a range of 1 to 16 to generate the reference frequency. This offers a finer
multiplication granularity. The PLL can multiply this reference clock by a
multiple of 2, 4, 6, ...,126,128 based on the SYNR register.
ėēēĊēĒ = ù × ĖĚĊĊēĒ × _[--^[-_ę--^Ě-_Č--^Ġ--_č-^ĕ--_ċ--^ę-_ĝ---+--+---^ø--_ø-^]---_]
NOTE:
Although it is possible to set the two dividers to command a very high
clock frequency, do not exceed the specified bus frequency limit for the
MCU. If PLLSEL=1, Bus Clock = PLLCLK/2.
The PLL is a frequency generator that operates in either acquisition
mode or tracking mode, depending on the difference between the output
frequency and the target frequency. The PLL can change between
acquisition and tracking modes either automatically or manually.
The VCO has a minimum operating frequency, which corresponds to the
self clock mode frequency f_SCM.
EXTAL
XTAL
REDUCED
CONSUMPTION ^OSCCLK
OSCILLATOR
REFDV <3:0>
REFERENCE
LOCK
FEEDBACK DETECTOR
LOCK
REFERENCE
PROGRAMMABLE
DIVIDER
PDET
PHASE
DETECTOR
VDDPLL/VSSPLL
UP
DOWN ^CPUMP
VCO
CLOCK
MONITOR
supplied by:
VDDPLL/VSSPLL
VDD/VSS
LOOP
PROGRAMMABLE
DIVIDER
SYN <5:0>
VDDPLL
LOOP
FILTER
XFC
PIN
PLLCLK
Figure 46 PLL Functional Diagram
PLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference
programmable divider and is divided in a range of 1 to 16 (REFDV+1) to
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1