MC9S12T64 Datasheet, PDF (179/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Resets and Interrupts
Effects of Reset
bits are set to mask any interrupt requests. The S bit is also set to inhibit
the STOP instruction.
Memory
After reset, the internal register block is located from $0000 to $03FF,
RAM is at $0800 to $0FFF and CALRAM is at $1000 to $17FF. In single
chip mode 64K byte FLASH EEPROM module is located from $0000 to
$FFFF.
Other Resources
The enhanced capture timer (ECT), pulse width modulation timer
(PWM), serial communications interfaces (SCI0 and SCI1), serial
peripheral interfaces (SPI), and analog-to-digital converters (ATD) are
off after reset.
NOTE:
When the MCU starts in the special single chip mode, the INITCRM and
PPAGE registers are overwritten by the secure BDM firmware. The CPU
registers also overwritten by the firmware. These overwritten values are
unknown and not guaranteed.
Resets and Interrupts
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1