MC9S12T64 Datasheet, PDF (161/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Functional Description
Functional Description
There are four main sub-blocks within the MEBI: external bus control,
external data bus interface, control and registers.
External Bus
Control
The external bus control generates the miscellaneous control functions
(pipe signals, ECLK, LSTRB and R/W) that will be sent external on Port
E, bits 6-2. It also generates the external addresses.
External Data Bus
Interface
The external data bus interface block manages data transfers from/to
the external pins to/from the internal read and write data buses. This
block selectively couples 8-bit or 16-bit data to the internal data bus to
implement a variety of data transfers including 8-bit, 16-bit, 16-bit
swapped and 8-bit external to 16-bit internal accesses. Modes,
addresses, chip selects, etc. affect the type of accesses performed
during each bus cycle.
Control
The control block generates the register read/write control signals and
miscellaneous port control signals.
Registers
The register block includes the fourteen 8-bit registers and five reserved
register locations associated with the MEBI sub-block.
Detecting Access
Type from External
Signals
The external signals LSTRB, R/W, and A0 indicate the type of bus
access that is taking place. Accesses to the internal RAM module are the
only type of access that produce LSTRB = A0 = 1, because the internal
RAM (except CALRAM) is specifically designed to allow misaligned
16-bit accesses in a single cycle. In these cases the data for the address
that was accessed is on the low half of the data bus and the data for
address + 1 is on the high half of the data bus.
Multiplexed External Bus Interface (MEBI)
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MC9S12T64Revision 1.1.1