MC9S12T64 Datasheet, PDF (541/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
Functional Description
the pin be driven high no later that eight target clock cycles after the
falling edge for a logic 1 transmission.
Since the host drives the high speedup pulses in these two cases, the
rising edges look like digitally driven signals.
CLOCK
TARGET SYSTEM
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START OF BIT TIME
SYNCHRONIZATION
UNCERTAINTY
TARGET SENSES BIT
10 CYCLES
Figure 104 BDM Host-to-Target Serial Bit Timing
EARLIEST
START OF
NEXT BIT
The receive cases are more complicated. Figure 105 shows the host
receiving a logic 1 from the target MCU. Since the host is asynchronous
to the target MCU, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit
time in the target MCU. The host holds the BKGD pin low long enough
for the target to recognize it (at least two target clock cycles). The host
must release the low drive before the target MCU drives a brief high
speedup pulse seven target clock cycles after the perceived start of the
bit time. The host should sample the bit level about 10 target clock cycles
after it started the bit time.
Fast Background Debug Module (FBDM)
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MC9S12T64Revision 1.1.1